The present invention relates to a semiconductor device and a control method thereof, and to, for example, a semiconductor device and a control method thereof that are suitable for executing desired processing without skipping low-priority processing.
Published Japanese Translation of PCT International Publication for Patent Application, No. 2009-542098 discloses an element controller for a resilient integrated circuit architecture. This integrated circuit includes a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element includes a selected circuit element which may vary by element interface and element type, and which may be configurable. The state machine element assigns various functions based on an element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element reassigns the first configuration to another composite circuit element and creates a second data link for continuing the same functioning. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the integrated circuit to continue the same functioning despite defects which may arise during operation.